Issue 14874: MARTE-AADL software concept upgrades (marte-rtf)
Source: THALES (Dr. Madeleine Faugere, madeleine.faugere(at)thalesgroup.com)
Nature: Clarification
Severity: Significant
Summary: The provide a full MARTE AADL alignment, upgrade platform concepts with AADL 1) virtual bus 2) virtual processor concepts
Resolution: Renumber section 2.4.4 in 2.4.6 Device
Add section 2.4.2 Virtual Processor
A virtual processor represents a logical resource that is capable of scheduling and
executing threads and other virtual processors bound to them. It will be represented as a
MARTE “swSchedulingResource” AND “ProcessingResource” stereotyped UML
Classifier
Add section 2.4.4 Virtual Bus
A virtual bus component represents logical bus abstraction such as a virtual channel or
communication protocol. It will be represented at resource level as a MARTE
“CommunicationMedia” stereotyped UML connection or classifier allocated to the
physical HWBus.
• If the communication media represents a bus, and the clock is the bus speed, "element size" would be the width of the bus, in bits.
• If the communication media represents a layering of protocols, "element size"
would be the frame size of the uppermost protocol.
Disposition: Resolved
Revised Text: for image(s) see page 68 of ptc/2010-08-30
Actions taken:
December 17, 2009: received issue
January 14, 2011: closed issue
Discussion: 

End of Annotations:=====

m: webmaster@omg.org
Date: 17 Dec 2009 04:59:15 -0500
To: <issues@omg.org>
Subject: Issue/Bug Report


*******************************************************************************
Name:          Madeleine Faugere
Company:       Thales
mailFrom:      madeleine.faugere@thalesgroup.com
Notification:  Yes
Specification: UML Profile for MARTE, v1.0
Section:       A.2.4
FormalNumber:  formal/09-11-02
Version:       1.0
RevisionDate:  11/2009
Page:          387
Title:         MARTE-AADL software concept upgrades
Nature:        Clarification
Severity:      Significant
test:          3qw8
B1:            Report Issue


Description:

The provide a full MARTE AADL alignment, upgrade platform concepts with AADL 1) virtual bus 2) virtual processor concepts